selected publications

G. Gopalakrishnan, D. R. Smith, & M. K. Srivas, ``An Algebraic Approach to the Specification and Synthesis of Digital Designs", 7th Intl. Symp. on Computer Hardware Description Languages and their Applications, Tokyo, Japan, Aug 29-31, 1985.

Awad N., Lin J, Sathianathan R. and Smith D.R., ``Timing Validation of Hardware Descriptions'', Proc Int'l workshop on Formal Methods in VLSI, Jan. 9-11 1991, Miami, Fla.

Smith, D. R., and J. C. Lin, ``The Treematch Chip'', IEEE Trans. Computers, V40:5 (May 1991), pp 629-639.

Awad, N., & D. R. Smith, ``Automatic Interfacing of Synchronous Modules to an Asynchronous Environment'', VLSI-91, International Conference on Very Large Scale Integration, Edinburgh, Scotland, August 1991.

Ramesh Sathianathan, & David R. Smith, ``A specification driven hierarchical test methodology'', Proc 6th Intl ASIC conference, October 1993.

D. R. Smith, ``A writing style for architectural synthesis'' Proc. 4th International Verilog HDL Conference, March, 1995.

D. R. Smith, ``Hardware synthesis from Ecapsulated Verilog Modules'', Intl. Conf on Application-Specific Systems, Achitectures, and Processors, Chicago, Ill, Aug 1996.

D. R. Smith, ``Verilog writing styles for hardware synthesis'', Prentice_hall, 2000.