A book for both students and professionals to speed their way through the steep learning curve of today's hardware synthesis technology.
Unlike professional books which concentrate on the operation of industrial tools and strategies for their use, this is a pedagocical text which leads its readers from first principles of hardware specification and design. Yet unlike academic texts which focus on the hardware design language and simulation, this text considers the synthesis subset and synthesis requirements from the outset. And unlike both, it includes a rich selection of complete realistic design examples, together with sufficient details of design flow and tool scripts so that readers using this book alone can quickly access the tools (Verilog, Synopsys, Altera, and Xilinx in this case) without recourse to large numbers of manuals.
Another particular emphasis of the text is the economy of specification writing and of writing styles . Except for the chapter on large designs, all example specifications are small enough to fit on a single page or less. In general we believe that an economical specification is likely to be closer to correctness and easier to debug. Nowadays the quality of the final synthesized result depends totally on the original specification, and different types of projects benefit from different writing styles. Among the styles considered here are the explicit style with separated controller and data path, implicit styles with one controller per synchronous block, the control-point style facilitating submodule re-use, and behavioral compiler styles. Separate chapters deal with synthesis to standard cell and gate arrays, and a final chapter discusses the significance of the trends toward mixed digital-analog and hardware-software design.
David R. Smith Department of Computer Science
State University of New York at Stony Brook
Stony Brook, NY 11794-4400
Email: drs@cs.sunysb.edu
Paul Franzon Dept ECE, Box 7914, North Carolina State University
Raleigh NC 27695-7914
Email: paulf@eos.ncsu.edu